US 2012/0269007 A1 · SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING OUT THE SAME

Abstract

A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.

Claims17

Dependent claims

A semiconductor memory device, comprising:

a memory cell array comprising a plurality of memory cells coupled in series between a bit line and a common source line;
peripheral circuits configured to read out data stored in a memory cell, selected from among the plurality of memory cells, by sequentially applying a plurality of read voltages to a word line, coupled to the selected memory cell, in a read operation;
and
a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the plurality of read voltages is applied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are applied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.

1 more element

A method of reading out data stored in a semiconductor memory device, the method comprising:

storing first normal data in a main latch unit of a page buffer by applying a first read voltage to a word line coupled to a memory cell and by sensing a voltage level of a bit line coupled to the memory cell;
storing second normal data in the main latch unit in which the first normal data is stored so that the second normal data is overlapped with the first normal data, by applying a second read voltage to the word line and by sensing a voltage level of the bit line;
transferring the second normal data to a cache latch unit of the page buffer and storing the second normal data in the cache latch unit;
storing over-sampling data in the main latch unit by sequentially applying a third read voltage lower than the first read voltage, a fourth read voltage higher than the first read voltage, a fifth read voltage lower than the second read voltage, and a sixth read voltage higher than the second read voltage to the word line and by sensing voltage levels of the bit line;
outputting the second normal data of the cache latch unit to a data line;
and
transferring the over-sampling data of the main latch unit to the cache latch unit and then outputting the over-sampling data to the data line.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device and method of reading out the same

Life of this patent

Semiconductor memory device and method of reading out the same

Life of this patent

Abstract

Claims17