US 2012/0268996 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device includes a memory cell array including memory block groups each coupled to bit lines, a page buffer group coupled to first bit lines of a first memory block group and configured to control voltages of the first bit lines of the first memory block group depending on data to be stored in memory cells in a program operation and configured to sense the voltage of the first bit lines in a read operation, at least one bit line coupling circuit configured to couple first bit lines of a nth memory block group to the page buffer group by selectively coupling first bit lines of the first to nth memory block groups in response to bit line coupling signals, and bit line control circuits configured to control second bit lines of the memory block groups in response to bit line control signals.

Claims30

Dependent claims

A semiconductor memory device, comprising:

a memory cell array comprising two or more memory block groups each coupled to bit lines;
a page buffer group coupled to first bit lines of a first memory block group and configured to control voltages of the first bit lines of the first memory block group depending on data to be stored in memory cells in a program operation and configured to sense the voltage of the first bit lines in a read operation;
at least one bit line coupling circuit configured to couple first bit lines of a nth memory block group, selected from among the memory block groups, to the page buffer group by selectively coupling first bit lines of the first to nth memory block groups in response to bit line coupling signals;
and
bit line control circuits configured to control second bit lines of the memory block groups in response to bit line control signals.

2 more elements

A semiconductor memory device, comprising:

two or more memory block groups each comprising memory strings coupled between a common source line and respective bit lines;
a page buffer group configured to control voltages of first bit lines of a memory block group, selected from among the memory block groups, depending on data to be stored in memory cells coupled to the first bit lines in a program operation and configured to sense the voltage of the first bit lines in a read operation;
at least one bit line coupling circuit configured to couple the first bit lines of the selected memory block group to the page buffer group in response to bit line coupling signals;
and
two or more bit line control circuits configured to couple second bit lines of the selected memory block group to the common source line thereof and control voltages of second bit lines of memory blocks remaining among the memory block groups depending on the program operation and the read operation in response to the bit line control signals.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims30