Nonvolatile memory device including memory cell array with upper and lower word line groups

A nonvolatile memory device comprising:

• a substrate;
• and
• a memory cell array comprising a plurality of cell strings, each cell string of the plurality of cell strings comprising at least one ground select transistor, a plurality of memory cells and at least one string select transistor that are stacked in a direction perpendicular to the substrate,
• wherein the plurality of memory cells are located at intersections of a plurality of word lines and a plurality of bit lines, and
• wherein a number of data bits stored in memory cells connected to word lines in an upper word line group is different from a number of memory cells connected to word lines in a lower word line group.

A nonvolatile memory device comprising:

• a memory cell array comprising a plurality of memory cells located at intersections of a plurality of word lines and a plurality of bit lines, wherein a number of data bits stored in memory cells connected to word lines in an upper word line group is different from a number of data bits stored in memory cells connected to word lines in a lower word line group, and wherein one of the upper word line group and the lower word line group includes memory cells which store a number of data bits that is not an integer;
• and
• a memory controller configured to perform multi-dimensional modulation for storing a data stream from a host in a memory cell group corresponding to the one of the upper word line group and the lower word line group including the memory cells which store the number of data bits that is not an integer,
• wherein a number of logic states of each of the memory cells in the memory cell group is two raised to the power of the number of data bits stored therein, and a total number of logic states of the memory cell group is the number of logic states of each memory cells raised to the power of the number of memory cells in the memory cell group.