Wafer-leveled chip packaging structure and method thereof

A semiconductor stacking packaging structure, comprising:

• a wafer having a first surface, a second surface, a first free end, a second free end, an integrated circuit pattern and a plurality of pads are formed on the first surface, a first half of the through hole and a second half of the through hole respectively penetrating the first free end and the second free end of the wafer, wherein the first free end and the second free end positioned in the both free end of the wafer respectively;
• a first insulating layer disposed on said first surface of said wafer, said first insulating layer having a plurality of first conductive vias penetrating said first insulating layer, wherein said first insulating layer covers a plurality of first chips, said integrated circuit pattern and said first surface of said wafer;
• a second insulating material is filled in the first half of the through hole and the second half of the through hole of said wafer respectively;
• at least one second conductive via include a third conductive via and a fourth conductive via, the third conductive via and the fourth conductive via passes through the second insulating material in the first half of the through hole and the second insulating material in the second half of the through hole respectively, the third conductive via and the fourth conductive via respectively connected to the first conductive vias;
• a plurality of solder balls or needle pins are soldered to the third conductive via and the fourth conductive via;
• the plurality of first chips mounted on the first surface of the wafer, wherein each of said plurality of first chips has at least one pad mounted on the surface of the first chip opposite to the wafer;
• a conductive pattern layer formed on a surface of the first insulating layer opposite to the wafer, and the conductive pattern layer is electrically connected with the first conductive via;
• a third insulating layer having a pattern formed on a surface of the first conductive pattern layer which is opposite to the first insulating layer;
• and
• a metallic film formed on an inner surface of the third conductive via and the fourth conductive via, the metallic film extended from along the second surface of the wafer to a limited area;
• wherein the second insulating material extended from along the second surface of the wafer to a limited area.