Vertical memory devices and methods of manufacturing the same

A vertical memory device, comprising:

• a plurality of conductive lines spaced apart from each other on a substrate in a vertical direction perpendicular to a top surface of a substrate;
• a plurality of insulation layer patterns, each disposed between two consecutive conductive lines;
• and
• a channel disposed on the top surface of the substrate and extending in the vertical direction through the plurality of lines and the plurality of insulation layer patterns,
• wherein the channel includes at least a first laterally recessed portion at a first vertical level and at least a first laterally non-recessed portion at a second vertical level.

A method of manufacturing a vertical memory device, the method comprising:

• forming a plurality of sacrificial layers and first insulation layers alternately and repeatedly on a substrate in a first direction;
• forming a first opening through the plurality of sacrificial layers and first insulation layers to expose a top surface of the substrate;
• forming a channel layer in the first opening and on the substrate;
• forming a second opening through the plurality of sacrificial layers and first insulation layers to expose a top surface of the substrate, wherein the second opening is located adjacent to the first opening in a second direction perpendicular to the first direction;
• removing the sacrificial layers to form a plurality of gaps between the plurality of first insulation layers to expose outer sidewalls of the channel layer by the plurality of gaps;
• partially removing the exposed outer sidewalls of the channel layer to form recesses in the channel layer;
• and
• forming a plurality of conductive layers to fill the plurality of gaps.