Apparatus and method for handling of modified immediate constant during instruction translation

A method performed by a microprocessor having an instruction set architecture that defines at least one instruction comprising an immediate field, wherein the immediate field has a first portion specifying a first value and a second portion specifying a second value, wherein the instruction instructs the microprocessor to perform an operation which uses a constant value as one of its source operands, wherein the constant value is the first value rotated/shifted by a number of bits based on the second value, the method comprising:

• translating the at least one instruction into one or more microinstructions, wherein the microinstructions are encoded in a distinct manner from the manner in which instructions defined by the instruction set architecture are encoded, wherein said translating is performed by an instruction translator of the microprocessor;
• and
• executing the microinstructions generated by the instruction translator to generate a result defined by the instruction set architecture, wherein said executing is performed by an execution pipeline of the microprocessor;
• generating, by the instruction translator rather than the execution pipeline, the constant value from the first and second values for provision to the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline.

A microprocessor having an instruction set architecture that defines at least one instruction comprising an immediate field, wherein the immediate field has a first portion specifying a first value and a second portion specifying a second value, wherein the instruction instructs the microprocessor to perform an operation which uses a constant value as one of its source operands, wherein the constant value is the first value rotated/shifted by a number of bits based on the second value, the microprocessor comprising:

• an instruction translator, that translates the at least one instruction into one or more microinstructions;
• and
• an execution pipeline, that executes the microinstructions generated by the instruction translator to generate a result defined by the instruction set architecture;
• wherein, when a value of the immediate field is in a predetermined subset of values:
• the instruction translator translates the instruction into at least one microinstruction;
• the instruction translator, rather than the execution pipeline, generates the constant value from the first and second values;
• and
• the execution pipeline executes the at least one microinstruction using the constant value generated by the instruction translator as one of its source operands;
• and
• wherein, when the value of the immediate field is not in the predetermined subset of values:
• the instruction translator translates the instruction into at least first and second microinstructions;
• the execution pipeline, rather than the instruction translator, generates the constant value by execution of the first microinstruction;
• and
• the execution pipeline executes the second microinstruction by performance of the operation using the constant value generated by the execution of the first microinstruction as one of its source operands.

A method performed by a microprocessor having an instruction set architecture that defines at least one instruction comprising an immediate field, wherein the immediate field has a first portion specifying a first value and a second portion specifying a second value, wherein the instruction instructs the microprocessor to perform an operation which uses a constant value as one of its source operands, wherein the constant value is the first value rotated/shifted by a number of bits based on the second value, the microprocessor also having an instruction translator and an execution pipeline, the method comprising:

• determining whether a value of the immediate field is in a predetermined subset of values, by the instruction translator;
• when the value of the immediate field is in the predetermined subset of values:
• translating the instruction into at least one microinstruction, by the instruction translator;
• generating, by the instruction translator rather than the execution pipeline, the constant value from the first and second values;
• and
• executing the at least one microinstruction using the constant value generated by the instruction translator as one of its source operands, by the execution pipeline;
• and
• wherein, when the value of the immediate field is not in the predetermined subset of values:
• translating the instruction into at least first and second microinstructions, by the instruction translator;
• generating, by the execution pipeline rather than the instruction translator, the constant value by execution of the first microinstruction;
• and
• executing the second microinstruction by performance of the operation using the constant value generated by the execution of the first microinstruction as one of its source operands, by the execution pipeline.

A computer program product encoded in at least one computer readable storage medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor having an instruction set architecture that defines at least one instruction comprising an immediate field, wherein the immediate field has a first portion specifying a first value and a second portion specifying a second value, wherein the instruction instructs the microprocessor to perform an operation which uses a constant value as one of its source operands, wherein the constant value is the first value rotated/shifted by a number of bits based on the second value, the computer readable program code comprising:
• first program code for specifying an instruction translator, that translates the at least one instruction into one or more microinstructions, wherein the microinstructions are encoded in a distinct manner from the manner in which instructions defined by the instruction set architecture are encoded;
• and
• second program code for specifying an execution pipeline, that executes the microinstructions generated by the instruction translator to generate a result defined by the instruction set architecture;
• wherein the instruction translator, rather than the execution pipeline, generates the constant value from the first and second values for provision to the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline.