Heterogeneous isa microprocessor with shared hardware isa registers

A method for operating a microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs, the method comprising:

• setting a mode indicator to indicate whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program;
• storing x86 ISA architectural state in a plurality of hardware registers of the microprocessor when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions;
• and
• storing ARM ISA architectural state in the plurality of hardware registers when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions.

A computer program product encoded in at least one computer readable storage medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs, the computer readable program code comprising:
• first program code for specifying a mode indicator, that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program;
• and
• second program code for specifying a plurality of hardware registers, wherein when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state, wherein when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state.