Load multiple and store multiple instructions in a microprocessor that emulates banked registers

A method for operating a microprocessor that supports an instruction set architecture that specifies a plurality of processor modes and that specifies architectural registers associated with each of the plurality of processor modes and that specifies a load multiple instruction that instructs the microprocessor to load data from memory into one or more of the architectural registers specified by the load multiple instruction, the method comprising:

• for each of the architectural registers specified by the load multiple instruction:
• if the architectural register is currently in the first portion, loading data from memory into direct storage of the microprocessor;
• and
• if the architectural register is currently in the second portion, loading data from memory into the direct storage and then storing the data from the direct storage to the indirect storage;
• wherein the direct storage holds data associated with a first portion of the architectural registers and is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit;
• wherein the indirect storage holds data associated with a second portion of the architectural registers, wherein the indirect storage is incapable of directly providing the data associated with the second portion of the architectural registers to the at least one execution unit;
• wherein the architectural registers in the first and second portions vary dynamically based upon the current processor mode of the plurality of processor modes.

A microprocessor that supports an instruction set architecture that specifies a plurality of processor modes and that specifies architectural registers associated with each of the plurality of processor modes and that specifies a store multiple instruction that instructs the microprocessor to store data to memory from one or more of the architectural registers specified by the store multiple instruction, the microprocessor comprising:

• direct storage, that holds data associated with a first portion of the architectural registers and that is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit;
• indirect storage, that holds data associated with a second portion of the architectural registers, wherein the indirect storage is incapable of directly providing the data associated with the second portion of the architectural registers to the at least one execution unit;
• wherein the architectural registers in the first and second portions vary dynamically based upon the current processor mode of the plurality of processor modes;
• and
• wherein for each of the architectural registers specified by the store multiple instruction:
• if the architectural register is currently in the first portion, the microprocessor stores data to memory from the direct storage;
• and
• if the architectural register is currently in the second portion, the microprocessor loads data from the indirect storage to the direct storage and then stores the data to memory from the direct storage.

A method for operating a microprocessor that supports an instruction set architecture that specifies a plurality of processor modes and that specifies architectural registers associated with each of the plurality of processor modes and that specifies a store multiple instruction that instructs the microprocessor to store data to memory from one or more of the architectural registers specified by the store multiple instruction, the method comprising:

• for each of the architectural registers specified by the store multiple instruction:
• if the architectural register is currently in the first portion, storing data to memory from direct storage of the microprocessor;
• and
• if the architectural register is currently in the second portion, loading data from the indirect storage to the direct storage and then storing the data from the indirect storage to memory;
• wherein the direct storage holds data associated with a first portion of the architectural registers and is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit;
• wherein the indirect storage holds data associated with a second portion of the architectural registers, wherein the indirect storage is incapable of directly providing the data associated with the second portion of the architectural registers to the at least one execution unit;
• wherein the architectural registers in the first and second portions vary dynamically based upon the current processor mode of the plurality of processor modes.

A computer program product encoded in at least one computer readable storage medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor that supports an instruction set architecture that specifies a plurality of processor modes and that specifies architectural registers associated with each of the plurality of processor modes and that specifies a load multiple instruction that instructs the microprocessor to load data from memory into one or more of the architectural registers specified by the load multiple instruction, the computer readable program code comprising:
• first program code for specifying direct storage, that holds data associated with a first portion of the architectural registers and that is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit;
• and
• second program code for specifying indirect storage, that holds data associated with a second portion of the architectural registers, wherein the indirect storage is incapable of directly providing the data associated with the second portion of the architectural registers to the at least one execution unit;
• wherein the architectural registers in the first and second portions vary dynamically based upon the current processor mode of the plurality of processor modes;
• and
• wherein for each of the architectural registers specified by the load multiple instruction:
• if the architectural register is currently in the first portion, the microprocessor loads data from memory into the direct storage;
• and
• if the architectural register is currently in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage.