Designed-based yield management system

An integrated-circuit yield improvement system, comprising:

• a defect signature library that stores defect signatures;
• and
• one or more computer processors comprising:
• a global signature analysis/grouping module configured to receive an integrated circuit (IC) design and identify areas in the IC design that include potential defect signatures based on the defect signatures stored in the defect signature library, wherein the global signature analysis/grouping module is configured to produce a global signature map indicating these areas and their associated potential defect signatures in the IC design;
• a local signature analysis/grouping module configured to receive the IC design, wherein the local signature analysis and grouping module is configured to identify and group local defect signatures in the IC design using the process monitoring and yield data as input, to output grouped local signatures;
• a filter and risk ranking module configured to identify killer defect signatures and filter out nuisance defects from the grouped local signatures and configured to output defects of interest comprising the killer defects;
• and
• an intelligent learning engine configured to analyze the global signature map and the grouped local signatures for each location, and to store, in the defect signature library, some of the defect signatures in the global signature map and the grouped local signatures, wherein the integrated-circuit yield improvement system is configured to output parameters for setting IC manufacturing process based on the global signature map and the grouped local signatures, wherein the intelligent learning module is configured to produce rules for filtering defect signatures, wherein the filter and risk ranking module configured to filter out defects from the grouped local signatures based on the rules.

A computer-implemented method for improving manufacturing yield in an integrated circuit, comprising:

• receiving an integrated circuit (IC) design in one or more computer processors that include a global signature analysis/grouping module, a local signature analysis/grouping module, and an intelligent learning engine, wherein the one or more computer processors are in communication with a defect signature library;
• identifying, by a global signature analysis/grouping module, areas in the IC design that include potential defect signatures based on the defect signatures stored in the defect signature library;
• producing, by the global signature analysis/grouping module, a global signature map indicating these areas and their associated potential defect signatures in the IC design;
• identifying and grouping, by the local signature analysis and grouping module, local defect signatures in the IC design with the process monitoring and yield data as input, to output grouped local signatures;
• analyzing the global signature map and the grouped local signatures for each location by the intelligent learning engine;
• storing, in the defect signature library, by the an intelligent learning engine, some of the defect signatures in the global signature map and the grouped local signatures;
• and
• outputting parameters for setting IC manufacturing process based on the global signature map and the grouped local signatures.