Memory repair analysis apparatus, memory repair analysis method, and test apparatus
AssigneeAdvantest Corporation
InventorsMasaaki Kosugi, Seiji KOIKE
Life of this patent
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AssigneeAdvantest Corporation
InventorsMasaaki Kosugi, Seiji KOIKE
Estimating the term…
A memory repair analysis apparatus that performs a repair analysis on a memory under test, comprising a row-oriented fail number storage section that stores the number of fail cells in each row; a column-oriented fail number storage section that stores the number of fail cells in each column; a row-weighting storage section that, for each row, stores the total number of fail cells in each column containing a fail cell included in the row; a column-weighting storage section that, for each column, stores the total number of fail cells in each row containing a fail cell included in the column; and a determining section that determines which of spare row regions and spare column regions are to replace the fail cells.
A memory repair analysis apparatus that performs a repair analysis on a memory under test including spare row regions for repairing memory regions in a row direction and spare column regions for repairing memory regions in a column direction, the memory repair analysis apparatus comprising:
A method for performing a memory repair analysis on a memory under test including spare row regions for repairing memory regions in a row direction and spare column regions for repairing memory regions in a column direction, the method comprising:
Dependencies are inferred from the claim text.