Nonvolatile memory devices and methods of operating nonvolatile memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsEun Chu Oh, Hong Rak Son, KyoungLae Cho, Junjin Kong
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Abstract
Methods of operating nonvolatile memory devices including a plurality of cell strings each having at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor, the operating methods including receiving a command and an address, determining a voltage applying time in response to the input command and address, and applying a specific voltage to memory cells of cell strings corresponding to the input address during the determined voltage applying time.
Claims20
A method of operating a nonvolatile memory device, the method comprising:
- receiving a command and an address;
- determining a voltage applying duration in response to the received command and address;
- and
- applying a first voltage to memory cells of cell strings corresponding to the received address for the voltage applying duration.
A nonvolatile memory device, comprising:
- a memory cell array including a plurality of cell strings, each of the plurality of cell strings including at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor;
- an address decoder connected to a plurality of string selection transistors of the plurality of cell strings via a plurality of string selection lines, the address decoder connected to a plurality of memory cells of the plurality of cell strings via a plurality of word lines, and the address decoder connected to a plurality of ground selection transistors of the plurality of cell strings via a ground selection line;
- a reading/writing circuit connected to the plurality of string selection transistors of the plurality of cell strings via a plurality of bit lines;
- a voltage generator configured to generate a plurality of voltages;
- and
- a controller configured to adjust a voltage applying duration upon applying a voltage generated by the voltage generator to a plurality of memory cells of the memory cell array.
A method of operating a three-dimensional (3D) semiconductor array, the method comprising:
- applying a first voltage to a first semiconductor array of a plurality of semiconductor arrays for a first period of time, each of the plurality of semiconductor arrays including a portion of one vertical channel, the first period of time based on a width of the portion of the vertical channel included in the first semiconductor device.
Dependencies are inferred from the claim text.