US 2012/0257442 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device having a read word line, a write word line and a sub-word driver operable to select the read word line using a main word signal and an inverse read block signal. The sub-word line selects the write word line using the main word signal and an inverse write block signal. The sub-word driver has a first inverter circuit using the main word signal as an input and outputting the read word line. The sub-word driver has a first transistor having a drain, a source, and a gate connected to the read word line, a low potential power source, and the inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of the first inverter circuit, a power source, and the inverse write block signal, respectively, and can select the write word line.

Claims19

Dependent claims

A semiconductor memory device characterized by comprising:

a read word line;
a write word line;
and
a sub-word driver operable to select said read word line using a main word signal and an inverse read block signal and select said write word line using said main word signal and an inverse write block signal.

1 more element

A semiconductor memory device having a memory cell, characterized in that:

said memory cell comprises:
an inverter circuit having a first storage node and a second storage node, said inverter circuit using said second storage node as an input and said first storage node as an output;
a load transistor connected between a power source and said second storage node, said load transistor using said first storage node as an input;
holding control means connected to said second storage node;
and
one access transistor connected between a read bit line and said first storage node, wherein
the memory cell consists of five transistors,
said holding control means is formed by a different access transistor controlled by a write word line, and said different access transistor holds a level of said second storage node when the write word line has a first low level,
said different access transistor is connected to said second storage node and a write bit line, said one access transistor uses a read word line as an input, data on said first storage node are read in a reading cycle by said one access transistor, and data are written into said memory cell via said one access transistor and said different access transistor in a writing cycle, and
the semiconductor memory device further comprising a sense amplifier having another inverter circuit using said read bit line as an input, data reading means for transmitting an output of said another inverter circuit to a data line, first data writing means for transmitting data from said data line to said read bit line using a write enable signal, and second data writing means for transmitting inverse data of data from said data line to said read bit line using an inverse write enable signal.

7 more elements

A semiconductor memory device having a memory cell, characterized in that:

said memory cell comprises:
an inverter circuit having a first storage node and a second storage node, said inverter circuit using said second storage node as an input and said first storage node as an output;
a load transistor connected between a power source and said second storage node, said load transistor using said first storage node as an input;
holding control means connected to said second storage node;
and
one access transistor connected between a read bit line and said first storage node, wherein
the memory cell consists of five transistors,
said holding control means is formed by a different access transistor controlled by a write word line, and said different access transistor holds a level of said second storage node when the write word line has a first low level,
said different access transistor is connected to said second storage node and a ground potential, said one access transistor uses a read word line as an input, data on said first storage node are read in a reading cycle by said one access transistor, and data from said one access transistor are written into said first storage node while said different access transistor resets said second storage node at a low level to perform a data writing operation in a writing cycle, and
the semiconductor memory device further comprising a sense amplifier having another inverter circuit using said read bit line as an input, reading means for transmitting an output of said another inverter circuit to a data line, and data writing means for transmitting data from said data line to said read bit line using a write enable signal.

7 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims19