Memory device and semiconductor device using the same

A memory device comprising:

• a first memory cell and a second memory cell each comprising:
• a transistor;
• and
• a memory element to which charge with an amount in accordance with data is supplied from a data line through the transistor,
• wherein the first memory cell corresponds to a valid bit,
• wherein the second memory cell corresponds to a data field,
• wherein the charge with the amount in accordance with the data is supplied from a data line through the first transistor to the memory element, and
• wherein, in a period in which the first transistors are off, a potential of the data line of the first memory cell is lower than a potential of the data line of the second memory cell.

A memory device comprising:

• a first memory cell and a second memory cell each comprising:
• a transistor;
• and
• a memory element to which charge with an amount in accordance with data is supplied from a data line through the transistor,
• wherein the first memory cell corresponds to a valid bit,
• wherein the second memory cell corresponds to a data field,
• wherein a precharge potential applied to the data line of the first memory cell before the data is read is higher than a precharge potential applied to the data line of the second memory cell before the data is read, and
• wherein a digital value of the data is determined by comparing the precharge potential with a potential of the data line at the time of reading the data.

A memory device comprising:

• a first memory cell and a second memory cell each comprising:
• a transistor;
• and
• a memory element to which charge with an amount in accordance with data is supplied from a data line through the transistor;
• and
• a first logic circuit and a second logic circuit connected to the first memory cell and the second memory cell through the respective data lines, the first logic circuit and the second logic circuit each including a logic element,
• wherein the first memory cell corresponds to a valid bit,
• wherein the second memory cell corresponds to a data field, and
• wherein a precharge potential applied to the data line of the first memory cell before the data is read is lower than a precharge potential applied to the data line of the second memory cell before the data is read.