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US 2012/0257434 A1Published application
Configurable bandwidth memory devices and methods
AssigneeMicron Technology, Inc.
InventorJoe M. Jeddeloh
Life of this patent
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Abstract
Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.
Claims19
A memory device, comprising:
- a stack of memory dies, including a number of memory vaults;
- a logic die coupled to the stack of memory dies;
- a memory fabric control register selectably coupled to the number of memory vaults to select a number of vaults that operate synchronously for a single memory request.
A memory device, comprising:
- a stack of memory dies, including a number of memory vaults;
- a logic die coupled to the stack of memory dies;
- a memory fabric control register selectably coupled to the number of memory vaults to select a number of vaults that operate synchronously for a single memory request;
- and
- a buffered connection between an originating and/or destination device and the stack of memory dies.
2 more elements
A system, comprising:
- a stack of memory dies, including a number of memory vaults;
- a logic die coupled to the stack of memory dies;
- a switch selectably coupled to the number of memory vaults to dynamically select a number of vaults that operate synchronously for a single memory request during operation of the apparatus.
A method of setting memory bandwidth, comprising:
- selecting a first number of vaults to operate synchronously for a first single memory request;
- and
- selecting a second number of vaults to operate synchronously for a second single memory request.
Dependencies are inferred from the claim text.