Gate driving circuit and driving method thereof

A gate driving circuit, the gate driving circuit receiving a plurality of clock signals in a sequence and comprising a plurality of cascaded drive units sequentially outputting an output signal, each drive unit, said an nth drive unit, comprising:

• a first switch, comprising a control terminal and a first terminal receiving a first input signal, and a second terminal coupled to a node;
• a second switch, comprising a control terminal receiving a second input signal, a first terminal coupled to the node, and a second terminal coupled to a low voltage source;
• a third switch, comprising a control terminal and a first terminal receiving a third input signal, and a second terminal coupled to the node;
• a fourth switch, comprising a control terminal receiving a fourth input signal, a first terminal coupled to the node, and a second terminal coupled to the low voltage source;
• and
• a fifth switch, comprising a control terminal coupled to the node, a first terminal receiving a clock signal, and a second terminal outputting the output signal;
• wherein the first input signal and the third input signal are output signals of drive units adjacent to the nth drive unit;
• the second input signal and the fourth input signal are output signals of next but one drive unit to the nth drive unit;
• wherein a first-stage drive unit of the gate driving circuit receives a scan start signal and a scan end signal while a last-stage drive unit of the gate driving circuit receives the scan end signal and the scan start signal;
• wherein a second-stage drive unit of the gate driving circuit receives the scan start signal and a second last-stage drive unit of the gate driving circuit receives the scan end signal, or the second-stage drive unit of the gate driving circuit receives the scan end signal and the second last-stage drive unit of the gate driving circuit receives the scan start signal;
• wherein a driving direction of the gate driving circuit is reversed by reversing the sequence of the clock signals and exchanging the scan start signal and the scan end signal.