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US 2012/0256774 A1Published application
Method and apparatus for self-test of successive approximation register (sar) a/d converter
AssigneeFreescale Semiconductor, Inc.
InventorsSanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
Life of this patent
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Abstract
A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.
Claims14
A method for testing an analog to digital converter (ADC), the ADC including a capacitor array, wherein the capacitor array includes one or more binary weighted capacitors and an additional capacitor, the method comprising:
- selecting one of the binary weighted capacitors as a test capacitor;
- applying a first voltage to the first plate of the additional capacitor and the capacitors of the capacitor array that have capacitance less than the capacitance of the test capacitor;
- applying a second voltage to the first plate of the remaining capacitors of the capacitor array, wherein the remaining capacitors comprise the capacitor under test and the capacitors that have a capacitance greater than the capacitance of the capacitor under test;
- switching off the connection to a second plate of the one of more binary weighted capacitors;
- applying the first voltage to the capacitor under test and applying the second voltage to the capacitors that have capacitance less than the capacitance of the capacitor under test and the additional capacitor;
- running successive approximation to measure a binary code that corresponds to the generated residue voltage by the capacitor array, wherein the binary code represents the error in the value of the test capacitor;
- and
- comparing the binary code with a predetermined value to generate an ADC status signal, wherein the ADC status signal indicates at least one of a pass status or fail status of the ADC.
5 more elements
An analog-to-digital converter (ADC) for converting an analog signal to a digital signal, comprising:
- a capacitor array including a plurality of binary weighted capacitors and an additional capacitor, wherein each capacitor of the capacitor array has first and second plates;
- a test controller, connected to the capacitor array, for storing one or more test instructions for performing a test on the ADC;
- a first comparator, connected to the capacitor array and a third voltage terminal for comparing an output voltage received from the capacitor array with a third voltage.
- a successive approximation register (SAR), connected to the first comparator and the test controller, for measuring a binary code corresponding to the one or more binary weighted capacitors.
1 more element
An analog-to-digital converter (ADC) for converting an analog signal to a digital signal, comprising:
- a capacitor array, comprising:
- a plurality of binary weighted capacitors and an additional capacitor, wherein the capacitors of the capacitor array each have first and second plates;
- and
- a switching circuit for selectively connecting the binary weighted capacitors and the additional capacitors to first, second, third, fourth voltage terminals;
- a test controller, connected to the capacitor array, for storing one or more test instructions for performing test on the ADC, wherein the one or more test instructions are for controlling the switching circuit to selectively connect the capacitors to the first, second and third voltage terminals;
- a multiplexer, connected to the test controller and the capacitor array, for switching an operating mode of the capacitor array between a test mode and a normal mode, wherein the test mode is used to perform the test on the ADC and the normal mode is used for analog to digital conversion.
- a successive approximation register (SAR), connected to the capacitor array and the test controller, for measuring a digital code corresponding to the one or more binary weighted capacitors;
- a first comparator, connected to the capacitor array, the third voltage terminal, and SAR, for comparing an output voltage received from the capacitor array with the third voltage;
- and
- a second comparator, connected to the SAR and the test controller, for comparing the digital code with a predetermined value to generate an ADC status signal, wherein the ADC status signal indicates at least one of a pass status and a fail status.
7 more elements
Dependencies are inferred from the claim text.