Pseudo full-rate sense amplifier flip-flop for high-speed receiver front-end

An apparatus comprising:

• means for driving a first sample of an input signal on an output node during a first phase of a clock signal and providing a high impedance to the output node during a second phase of the clock signal;
• and
• means for providing a high impedance to the output node during a second phase of the clock signal and driving a second sample of the input signal on the output node during a first phase of the clock signal;
• wherein the input signal is sampled at a rate that is N times the rate of the clock signal, N being an integer greater than one.

A tangible computer-readable medium encoding a representation of an integrated circuit that comprises:

• a first sensing circuit operative to drive on a node during a first phase of a clock signal a first sample of an input signal, the first sensing circuit being inoperative during a second phase of the clock signal;
• and
• a second sensing circuit operative to drive on the node during the second phase of the clock signal a second sample of the input signal, the second sensing circuit being inoperative during the first phase of the clock signal,
• wherein a sampled signal on the node includes the first and second samples and has a bit rate that is N times the rate of the clock signal, N being an integer greater than one.