US 2012/0256310 A1 · SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes a multi-level wiring structure that includes a first wring layer, a plurality of first patterns, and a first mark. The first wring layer is disposed at a first wiring level of the multi-level wiring structure. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The first mark is disposed over the first wring layer. The first mark is disposed at a third wiring level. The third wiring level is above the second wiring level.

Claims20

Dependent claims

A semiconductor device comprising:

a multi-level wiring structure including:
a first wiring layer disposed at a first wiring level of the multi-level wiring structure;
a plurality of first patterns disposed over the first wring layer, the plurality of first patterns being disposed at a second wiring level of the multi-level wiring structure, the second wiring level being above the first wiring level;
and
a first mark disposed over the first wring layer, the first mark being disposed at a third wiring level of the multi-level wiring structure, the third wiring level being above the second wiring level.

2 more elements

A semiconductor device comprising:

a multi-level wiring structure including a first level wiring layer and a second level wiring layer formed over the first level wiring layer;
an insulation layer formed over the multi-level wiring structure and including a plurality of first openings and a second opening;
a plurality of bump electrodes each disposed in an associated one of the first openings;
a plurality of first wirings produced as the second level wiring layer, each of the first wirings being vertically arranged with an associated one of the first openings of the insulation layer, and each of the first wirings being coupled to an associated one of the bump electrodes;
a second wiring produced as the second level wiring layer and vertically arranged with the second opening of the insulation layer, and the second wiring being free from a contact with any one of the bump electrodes;
and
a plurality of third wirings produced as the first wiring layer and disposed in a first region that is vertically arranged with the first opening of the insulation layer.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims20