Memory device comprising an array portion and a logic portion
AssigneeMicron Technology, Inc.
InventorWerner Juengling
Life of this patent
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Abstract
In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.
Claims26
A memory device comprising:
- a substrate having an array portion and a logic portion;
- a first plurality of transistor devices including a plurality of semiconductor structures that are recessed in the array portion of the substrate, wherein a top surface of each of the plurality of semiconductor structures is substantially co-planar with a top surface of the substrate, and each of the plurality of semiconductor structures include a channel portion that is contiguous with the substrate array portion and adjacent to a gate region;
- and
- a second plurality of transistor devices formed over the logic portion of the substrate, wherein each of the second plurality of transistor devices include a gate oxide layer, a conductive gate layer, and sidewall spacer structures, wherein there is no dielectric layer between the sidewall spacer structures, and wherein the second plurality of transistor devices are formed in a layer that is above the plurality of semiconductor structures.
A partially-formed integrated circuit comprising:
- a first plurality of features comprising a first material and formed over a first portion of a substrate, wherein the first plurality of features are separated from each other by a first spacing;
- a second plurality of features comprising a second material and formed over a second portion of the substrate, wherein the first material is the same as the second material;
- a gap fill structure positioned between and contacting a selected two of the first plurality of features;
- and
- a plurality of sidewall spacers positioned adjacent the second plurality of features, wherein adjacent sidewall spacers are separated from each other by a separation region, and wherein the plurality of sidewall spacers and the gap fill structure comprise the same material.
Dependencies are inferred from the claim text.