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US 2012/0256180 A1Published application
Method of evaluating a semiconductor wafer dicing process
AssigneeSTMicroelectronics (Rousset) SAS
InventorFrancois Tailliet
Life of this patent
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Abstract
Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process.
Claims21
A method of evaluating a semiconductor wafer dicing process, the method comprising:
- providing evaluation lines extending in a scribe line of the wafer;
- dicing the wafer in the scribe line;
- evaluating information regarding lengths of the evaluation lines;
- and
- using the information to evaluate the dicing process.
2 more elements
A semiconductor wafer comprising:
- evaluation lines extending in a scribe line of the wafer;
- and
- an integrated circuit connected to the evaluation lines, the integrated circuit comprising an evaluation circuit configured to evaluate information regarding lengths of each of the evaluation lines.
A semiconductor die comprising:
- an evaluation circuit;
- scribe line portions extending around a perimeter of the evaluation circuit;
- and
- evaluation lines extending into at least one of the scribe line portions, the evaluation circuit configured to evaluate information regarding lengths of the evaluation lines.
1 more element
(canceled)
Dependencies are inferred from the claim text.