US 2012/0240089 A1 · EVENT SCHEDULER FOR AN ELECTRICAL CIRCUIT DESIGN TO ACCOUNT FOR HOLD TIME VIOLATIONS

Abstract

Implementations of the present disclosure involve an apparatus and/or method for identifying and classify nodes of an electrical circuit design to account for hold time violations occurring within the circuit. The nodes may be ordered based on a criticality of the nodes that may aid in identifying those nodes of the circuit where hold time violations may be corrected. In one embodiment, the criticality may relate to the number of potentially violating paths that utilize the identified nodes such that corrective measures applied at those nodes may correct several hold time violating paths. In addition, criticality may be scaled utilizing an available buffer library and other timing information. Thus, by utilizing the methods and/or apparatuses of the present disclosure, the locations where timing violation corrective measures may be applied that improve or correct several violating data paths at once may be identified in such a manner so as to reduce the number of overall corrections made to the circuit design, reducing the cost and necessary time associated with the corrections.

Claims20

Dependent claims

A method for accounting for one or more hold time violations of an electrical circuit design, the method comprising:

analyzing an electrical circuit design to determine one or more hold time violations;
associating a criticality to one or more nodes of the electrical circuit design, the criticality relating to the number of hold time violations determined at the one or more nodes;
storing indicators of the one or more nodes and the associated criticality of the one or more nodes in a data set;
generating a change event queue to account for the one or more hold time violations based on the associated criticality of the one or more nodes in the data set;
and
altering the electrical circuit design based on the change event queue to account for the one or more hold time violations of the electrical circuit design.

3 more elements

A computing device for designing an electrical circuit comprising:

a processing device;
and
a computer-readable medium having stored thereon data representing sequences of instructions that, when executed by the processing device, cause the processing device to perform the operations of:
detecting one or more hold time violations of an electrical circuit design at one or more endpoints of the electrical circuit design;
tracing along at least one data path for each of the one or more hold time violations, the at least one data path comprising one or more nodes of the electrical circuit design;
computing a criticality for the one or more nodes of each of the at least one data paths, the criticality associated with the number of data paths associated with the one or more nodes;
creating a data set comprising indicators of the one or more nodes and the computed criticality of the one or more nodes;
ordering the data set based on the criticality of the one or more nodes;
generating a change event to add a delay component in the electrical circuit design at a first node of the one or more nodes in the data set;
and
adding the delay component to the electrical circuit design based on the change event.

8 more elements

Dependencies are inferred from the claim text.

Event scheduler for an electrical circuit design to account for hold time violations

Life of this patent

Event scheduler for an electrical circuit design to account for hold time violations

Life of this patent

Abstract

Claims20