Seamless interface for multi-threaded core accelerators

A system for interfacing between a multi-threaded processing core and a hardware accelerator, comprising:

• one or more processing units on the processing core configured for copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core;
• and
• a translation lookaside buffer (TLB) on the hardware accelerator and including one or more reserved entries for each of the threads operating on the processing core for simultaneously storing one or more of the memory address translations for each of said threads;
• whereby when any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for said any one of the threads to facilitate starting said specified operation without memory translation faults.

An article of manufacture comprising:

• at least one tangible computer readable medium having computer readable program code logic to execute machine instructions in one or more processing units for interfacing between a processing core and a hardware accelerator, wherein multiple threads operate on the processing core, said computer readable program code logic, when executing, performing the following:
• copying from the processing core to the hardware accelerator memory address translations for each of the multiple threads;
• and
• simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads;
• whereby when any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for said any one of the threads to facilitate starting said specified operation without memory translation faults.