Memory controller address and data pin multiplexing
AssigneeFreescale Semiconductor, Inc.
InventorsHemant Nautiyal, Dhruv Satsangi
Life of this patent
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Abstract
A system and a method for configuring a memory controller that communicates with a memory device muxes selected pins for the data transfer. The memory controller includes a set of pins where each pin of the set is associated with a data bit and an address bit. A programmable logic block is connected to the set of pins and uses a subset of the set of pins to enable data transfer between the memory device and the memory controller depending on the size of the memory device such that the pins not included in the subset are available for other applications.
Claims20
A system for configuring a memory controller that communicates with a memory device, the memory controller including a set of pins, each pin of the set of pins being associated with at least one of a data bit and an address bit, the system comprising:
- a programmable logic block connected to the set of pins of the memory controller, the programmable logic block using a subset of the set of pins to enable data transfer between the memory device and the memory controller in accordance with the size of the memory device, wherein the pins outside the subset are available for one or more other applications.
A system for configuring a memory controller, the memory controller suitable for communicating with a memory device, the memory controller including a set of pins, each pin of the set of pins being associated with at least one of a data bit and an address bit, the system comprising:
- a programmable logic block connected to the set of pins of the memory controller, the programmable logic block selecting a subset of the set of pins to enable data transfer between the memory device and the memory controller, wherein the selection of the subset is performed by re-organizing one or more address bits among the set of pins of the memory controller in accordance with the size of the memory device;
- a multiplexer connected to the programmable logic block for multiplexing address and data bits;
- and
- a latch connected between the multiplexer and the memory device, the latch latching the multiplexed address and data bits on a plurality of pins from the subset of pins to transfer address and data bits between the memory device and the memory controller.
A method for configuring a memory controller that communicates with a memory device, the memory controller including a set of pins, each pin of the set of pins being associated with at least one of a data bit and an address bit, the method comprising:
- selecting a subset of the set of pins to enable data transfer between the memory device and the memory controller, the selection of the subset being performed by re-organizing address bits among the set of pins of the memory controller in accordance with the size of the memory device;
- and
- multiplexing address bits and data bits on a plurality of pins of the subset of pins to transfer data between the memory device and the memory controller.
Dependencies are inferred from the claim text.