US 2012/0239874 A1Published application

Method and system for resolving interoperability of multiple types of dual in-line memory modules

AssigneeNetlist, Inc.

InventorsHyun Lee, Jayesh R. Bhakta, Paresh Sheth

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Abstract

Systems and methods are described for resolving certain interoperability issues among multiple types of memory modules in the same memory subsystem. The system provides a single data load DIMM for constructing a high density and high speed memory subsystem that supports the standard JEDEC RDIMM interface while presenting a single load to the memory controller. At least one memory module includes one or more DRAM, a bi-directional data buffer and an interface bridge with a conflict resolution block. The interface bridge translates the CAS latency (CL) programming value that a memory controller sends to program the DRAMs, modifies the latency value, and is used for resolving command conflicts between the DRAMs and the memory controller to insure proper operation of the memory subsystem.

Claims20

Dependent claims

A method to interface a memory module to a memory controller, the memory module comprising a plurality of programmable memory devices and an interface bridge, the interface bridge configured to receive from the memory controller any one of a first read command, a first write command, and a first programming command, the method comprising:

the interface bridge determining a first and second latency delay values;
the interface bridge receiving a first read command issued by the memory controller to the memory module, wherein the first read command is stored by the interface bridge;
the interface bridge transmitting to the plurality of memory devices the first read command, wherein the transmitting of the first read command is delayed using the first latency delay value;
the interface bridge receiving a first write command issued by the memory controller to the memory module, wherein the first write command is stored by the interface bridge;
and
the interface bridge transmitting to the plurality of memory devices the first write command, wherein the transmitting of the first write command is delayed using the second latency delay value.

3 more elements

A memory module comprising:

an interface bridge configured to (i) receive from a memory controller a first programming command to program a first latency value into a plurality of programmable memory devices, the first programming command includes the first latency value, (ii) generate a second latency value, wherein the second latency value is less than the first latency value, and (iii) program the second latency value into the plurality of programmable memory devices.

A method to interface a memory controller to a first and second memory modules, the first memory module comprising a first plurality of programmable memory devices and a first interface bridge, the first interface bridge configured to receive from the memory controller any one of a first read command and a first write command, the second memory module comprising a second plurality of programmable memory devices and a second interface bridge, the second interface bridge configured to receive from the memory controller any one of a second read command and a second write command, the method comprising:

determining a first latency delay value for the first read command, wherein the first read command is (i) issued by the memory controller to the first memory module, and (ii) stored by the first interface bridge;
the first interface bridge transmitting the first read command to the first plurality of programmable memory devices, wherein the transmitting of the first read command to the first plurality of programmable memory devices is delayed using the first latency delay value;
determining a second latency delay value for the first write command, wherein the first write command is (i) issued by the memory controller to the first memory module, and (ii) stored by the first interface bridge;
the first interface bridge transmitting the first write command to the first plurality of programmable memory devices, wherein the transmitting of the first write command to the first plurality of programmable memory devices is delayed using the second latency delay value;
the second interface bridge receiving and storing any one of the second read command and the second write command, wherein the memory controller issues any one of the second read command and the second write command to the second memory module;
and
the second interface bridge transmitting any one of the second read command and the second write command to the second plurality of programmable memory devices, wherein the transmitting of any one of the second read command and the second write command to the second plurality of programmable memory devices is delayed using a third latency delay value.

4 more elements

Dependencies are inferred from the claim text.