Methods and Apparatus for Memory Word Line Driver

An apparatus, comprising:

• a decoder circuit coupled to receive address inputs, and having a decoder output;
• and
• a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal;
• wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal.

A method, comprising:

• providing a word line decoder circuit coupled to address signals and outputting a decoder output;
• and
• coupling a word line clock gating circuit to the decoder output and to a word line clock signal, configured to output a word line pulse on a word line responsive to a an edge on the word line clock signal;
• wherein the address signals have a set up time requirement relative to the edge of the word line clock signal, and a zero or less hold time requirement relative to the edge of the word line clock signal.