Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system
AssigneeElpida Memory, Inc.
InventorAtsuo KOSHIZUKA
Life of this patent
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Abstract
A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal provided to receive a command that communicates the data with an outside thereof, and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.
Claims20
A semiconductor memory device, comprising:
- a clock terminal provided to receive a clock signal;
- a data terminal provided to transfer a data therethrough in synchronization with the clock signal;
- a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough;
- a command terminal provided to receive a command that communicates the data with an outside thereof;
- and
- an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.
The semiconductor memory device as claimed in claim
- wherein the length of the preamble is a second length different from the first length when the information indicates a second value different from the first value.
A semiconductor memory device, comprising:
- a first external terminal configured to receive a clock signal;
- a second external terminal configured to receive a read command in synchronization with the clock signal;
- a third external terminal configured to output a data strobe signal in response to the read command, the data strobe signal including a preamble and a toggle transition following to the preamble;
- a fourth external terminal configured to output a read data in synchronization with the toggle transition of the data strobe signal;
- a fifth external terminal configured to receive a preamble length information;
- and
- a control circuit configured to control a length of the preamble of the data strobe signal based on the preamble length information.
A semiconductor memory device, comprising:
- a first external terminal provided to receive a clock signal;
- a second external terminal provided to transfer a data therethrough in synchronization with the clock signal;
- a third external terminal provided to receive a command for communicating the data with an outside thereof;
- a control circuit configured to produce a data strobe signal, which includes a preamble and a toggle transition following to the preamble, so that the transferring the data is conducted by the toggle transition of the data strobe signal;
- and
- a fourth external terminal provided to be supplied an information specifying a length of the preamble of the strobe signal from an outside of the semiconductor memory device.
Dependencies are inferred from the claim text.