Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorMasahiro KAMOSHIDA
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Abstract
According to one embodiment, there is provided a semiconductor memory device including a memory cell array, a plurality of signal lines, and a plurality of signal-line-lead-out portions. In the memory cell array, a plurality of memory cells are arranged. The plurality of signal lines connected to the plurality of memory cells. The plurality of signal-line-lead-out portions are arranged in a periphery of the memory cell array and are connected to the plurality of signal lines. Each of the plurality of signal-line-lead-out portions includes a plug as an electrode whose upper surface and side surface are covered with a passivation film.
Claims20
A semiconductor memory device, comprising:
- a memory cell array in which a plurality of memory cells are arranged;
- a plurality of signal lines connected to the plurality of memory cells;
- and
- a plurality of signal-line-lead-out portions arranged in a periphery of the memory cell array and connected to the plurality of signal lines,
- wherein each of the plurality of signal-line-lead-out portions includes a plug as an electrode whose upper surface and side surface are covered with a passivation film.
Dependencies are inferred from the claim text.