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US 2012/0236640 A1Published application
Reducing effects of erase disturb in a memory device
AssigneeMicron Technology, Inc.
InventorsAkira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers
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Abstract
A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.
Claims20
A method for reducing erase disturb in a memory device, the method comprising:
- determining which group of word lines, of a plurality of word lines, to bias with a negative voltage wherein the group of word lines comprises less than all of the word lines of a series string of memory cells;
- biasing only the group of word lines with the negative voltage and remaining word lines of the series string of memory cells with a non-negative voltage;
- biasing a selected word line coupled to a selected memory cell of the series string of memory cells with a program voltage subsequent to biasing only the group of word lines with the negative voltage;
- and
- biasing other control gates of the string of memory cells with a pass voltage subsequent to the biasing the certain control gates with negative voltage.
2 more elements
A method for reducing erase disturb in a memory device, the method comprising:
- biasing, with a negative voltage, a first range of word lines on a source side of a selected memory cell of a series string of memory cells and a second range of word lines on a drain side of the selected memory cell, wherein the first and second ranges include less than all of the word lines of the series string;
- biasing, with a non-negative voltage and subsequent to biasing with the negative voltage, the first and second ranges of word lines;
- and
- applying at least one programming voltage pulse to a selected word line of the series string of memory cells subsequent to biasing with the negative voltage.
1 more element
A memory device comprising:
- a memory array comprising a plurality of memory cells;
- and
- memory control circuitry, configured to control the memory array, wherein the memory control circuitry is configured to control a bias of a subset of a plurality of control gates of a string of memory cells with a negative voltage and control a subsequent bias of the subset of the plurality of control gates of the string of memory cells with a non-negative voltage wherein the subset is less than all of the plurality of control gates of the string of memory cells.
Dependencies are inferred from the claim text.