Level Shifter Design

A device configured to receive a first input voltage signal at a first input node and a second input voltage signal at a second input node, and further produce an output comprising:

• a first inverter, configured to operate at a potential difference between a first voltage VP1 of the first inverter at a voltage VP1 signal node and a second voltage VP2 of the first inverter at a voltage VP2 signal node, the first inverter having an input terminal connected to the first input node of the device, and further having an output terminal;
• a first capacitor having a first terminal connected to the output terminal of the first inverter, and a second terminal;
• a first resistor having a first terminal connected to a third voltage VP3 of the first resistor at a voltage VP3 signal node and a second terminal;
• a first latch circuit, configured to operate at a potential difference between a fourth voltage VP4 of the first latch at a voltage VP4 signal node and a fifth voltage VP5 of the first latch at a voltage VP5 signal node, the latch having an input node connected to the second terminal of the first resistor and the second terminal of the first capacitor, and an output node;
• a first P-transistor, wherein the voltage VP5 signal node is connected to a first terminal of the first P-transistor while a second terminal of the first P-transistor is connected to a sixth voltage VP6 signal node of the first P-transistor, and a gate of the first P-transistor is connected to a seventh voltage VP7 signal node of the first P-transistor;
• a first latch output inverter with an input terminal connected to the output terminal of the first latch, and an output terminal, driven by voltages V8 and V9 at a voltage V8 signal node and a voltage V9 signal node respectively;
• a second P-transistor with its gate connected to the output terminal of the first latch output inverter, its first terminal connected a voltage V12 signal node, and its second terminal connected to the output of the device;
• a second inverter, configured to operate at a potential difference between a first voltage VN1 of the second inverter at a voltage VN1 signal node and a second voltage VN2 of the second inverter at a voltage VN2 signal node, the second inverter having an input terminal connected to a second input node of the device, and further having an output terminal;
• a second capacitor having a first terminal connected to the output terminal of the second inverter, and a second terminal;
• a second resistor having a first terminal connected to a third voltage VN3 of the second transistor at a voltage VN3 signal node and a second terminal;
• a second latch circuit, configured to operate at a potential difference between a fourth voltage VN4 of the second latch at a voltage VN4 signal node and a fifth voltage VN5 of the second latch at a voltage VN5 signal node, and further having an input node connected to the second terminal of the second resistor and the second terminal of the second capacitor, and an output node;
• a first N-transistor, wherein the voltage VN4 signal node is connected to a first terminal of the first N-transistor while a second terminal of the first N-transistor is connected to a sixth voltage VN6 signal node of the first N-transistor, and a gate of the first N-transistor is connected to a seventh voltage VN7 signal node of the first N-transistor;
• a second latch output inverter with an input terminal connected to the output of the second latch and an output terminal, driven by voltages V10 and V11 at a voltage V10 signal node and a voltage V11 signal node respectively;
• and
• a second N-transistor with its gate connected to the output terminal of the second latch output inverter, its first terminal connected a voltage V13 signal node, and its second terminal connected to the output of the device.

A method of operating a level shifter circuit configured to receive an input voltage signal and produce an output voltage signal comprising:

• receiving the input voltage signal by a first inverter operating at a potential difference between a first voltage V1 and a second voltage V2 and inverting the input voltage signal, with an output terminal connected to a first terminal of a capacitor;
• capacitively coupling the inverted input voltage signal by the capacitor to an input of a latch circuit;
• maintaining a desired voltage on the input of the latch by coupling the input of the latch to a voltage source via a resistor;
• and
• generating the output voltage signal by the latch operating at a potential difference between a fourth voltage V4 and a fifth voltage V5.