US 2012/0235302 A1Published application

Semiconductor device manufacturing method and semiconductor device

AssigneeRenesas Electronics Corporation

InventorAkira FURUYA

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Abstract

A semiconductor manufacturing method includes: forming a seed film including a first metal over a bottom surface and a side wall of an opening portion formed over interlayer insulating films and a field portion located over the interlayer insulating film except the opening portion, forming a resist over the seed film and filling the opening portion with the resist, removing part of the resist, exposing the seed film formed over the upper portion of the side walls of the opening portion and the field portion, forming a cover film including a second metal, whose resistivity is higher than that of the first metal, over the seed film located over the upper portion of the side wall of the opening portion and the field portion, exposing the seed film by removing the resist, and forming a plating film including the first metal over the exposed seed film.

Claims16

Dependent claims

A semiconductor device manufacturing method comprising:

forming a seed film including a first metal over a bottom surface and a side wall of an opening portion formed over an insulating film and the insulating film except for the opening portion;
forming a mask film over the seed film and filling the opening portion with the mask film;
removing a part of the mask film while leaving the mask film over the seed film formed over the bottom surface of the opening portion and exposing the seed film, which is formed over an upper portion of the side wall of the opening portion and the insulating film except for the opening portion;
forming a cover film including a second metal whose resistivity is higher than that of the first metal over the seed film located over the upper portion of the side wall of the opening portion and the insulating film except for the opening portion;
exposing the seed film by removing the mask film left over the opening portion after forming the cover film;
and
forming a plating film including the first metal over the exposed seed film.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/398,363Filed 16 Feb 2012
Priority: JP 2011-05921617 Mar 2011
Published: 20 Sep 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 20/40
Interconnections in chips, wafers or substrates: interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or…
H10W 20/035
In openings in dielectrics: combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
H10W 20/036
In openings in dielectrics: the barrier, adhesion or liner layers being within a main fill metal
H10W 20/037
In openings in dielectrics: the barrier, adhesion or liner layers being on top of a main fill metal

Family

US 8,652,966 B2Related patent
US 2012/0235302 A1This patent

From the US filing history. Foreign family members aren’t listed.

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