High density six transistor finfet sram cell layout
AssigneeInternational Business Machines Corporation
InventorAbhisek Dixit
Life of this patent
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Abstract
Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout.
Claims20
An integrated circuit logic element or component including FinFETS comprising
- two pairs of parallel fins which are oriented in orthogonal directions to each other wherein each fin of said two pairs of parallel fins has impurities implanted therein of the same or different conductivity types such that said two pairs of parallel fins can function as two, three or four transistors,
- a gate structure common to each pair of fins, and
- connections between said two, three or four transistors.
An SRAM bit-cell layout comprising
- two pairs of complementary FinFETs proximate to opposing sides of an area of said bit cell, each said pair of complementary transistors comprising two parallel fins and having a common gate and a common node to function as an inverter,
- two pass FinFET transistors, each of said two pass FinFET transistors being proximate to one of two other opposing sides of said area of said bit cell and formed of two parallel fins oriented orthogonally to said parallel fins of said two pairs of complementary FinFETs, and
- connections between said two pairs of complementary FinFETs.
A method of forming an integrated circuit comprising steps of
- patterning a sacrificial layer on a substrate to form a structure having a prism shape,
- forming sidewalls on a periphery of said structure having a prism shape,
- removing said structure having a prism shape selectively to said sidewalls,
- forming further sidewalls on inner and outer sides of said sidewalls,
- removing said sidewalls selectively to said further sidewalls to form two concentric patterns, and
- transferring said two concentric patterns to said substrate to form a pair of concentric structures.
A method of forming an integrated circuit comprising steps of
- forming at least two pairs of semiconductor fins on a substrate,
- implanting impurities of a first conductivity type preferentially in a first fin of a pair of said fins, and
- implanting impurities of a second conductivity type preferentially in a second fin of said pair of fins.
Dependencies are inferred from the claim text.