Structure and method of forming a transistor with asymmetric channel and source/drain regions
AssigneeInternational Business Machines Corporation
InventorsHaining S. Yang, Kangguo Cheng, Robert Wong
Life of this patent
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Abstract
A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material.
Claims22
A semiconductor structure comprising:
- a semiconductor substrate;
- a conductive gate abutting a gate insulator for controlling conduction of a channel region, wherein said gate insulator abuts said channel region;
- and
- a source region and a drain region associated with said conductive gate,
- wherein said source region includes a first material and said drain region includes a second material, and
- wherein said conductive gate is self-aligned to said first and said second material.
An asymmetric transistor formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer, a buried insulating (BOX) layer and a substrate layer, the asymmetric transistor comprising:
- a SiGe layer formed adjacent to a portion of said SOI layer;
- a channel region formed over said SOI layer and being associated with said asymmetric transistor;
- and
- a conductive gate formed over said channel region;
- and
- a source region and a drain region formed adjacent to either side of said channel region,
- wherein said source region is formed in at least one of said SOI layer and said SiGe layer and said drain region is formed in at least one of said SOI layer and said SiGe layer, and
- wherein said conductive gate is self-aligned to said SOI layer and said SiGe layer.
A semiconductor device comprising:
- a field effect transistor comprising:
- a channel formed in a first portion of a SOI layer of a semiconductor substrate;
- a metal gate disposed above said channel;
- and
- a source region and a drain region formed on a portion of said SOI layer and in a recess at each end of said channel;
- wherein said source region includes a first material;
- and wherein said drain region includes a second material, and
- wherein said metal gate is self-aligned to said first and said second material.
A method of forming a semiconductor device formed over a semiconductor substrate, the method comprising:
- epitaxially growing a SiGe layer in a portion of a semiconductor-on-insulator (SOI) layer of said semiconductor substrate;
- and
- forming a transistor over said SOI layer, wherein said forming of said transistor includes:
- forming a channel region in a first portion of said SOI layer;
- forming a metal gate above said channel region;
- and
- forming a source region and a drain region formed between said channel region;
- wherein said source region is formed in at least one of said SOI layer and said SiGe layer;
- and further wherein said drain region is formed in at least one of said SOI layer and said SiGe.
Dependencies are inferred from the claim text.