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US 2012/0235228 A1Published application
Transistor structure and method for preparing the same
AssigneeNanya Technology Corporation
InventorsChin Ling Huang, Tieh Chiang Wu
Life of this patent
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Abstract
A buried channel transistor structure includes a semiconductor substrate; a conductive block positioned in the semiconductor substrate; a gate dielectric layer positioned between the conductive block and the semiconductor substrate; and a bulge-shaped dielectric structure positioned on the conductive block and the gate dielectric layer.
Claims17
A transistor structure, comprising:
- a semiconductor substrate;
- a conductive block positioned in the semiconductor substrate;
- a gate dielectric layer positioned between the conductive block and the semiconductor substrate;
- and
- a bulge-shaped dielectric structure positioned on the conductive block and the gate dielectric layer.
2 more elements
A method for preparing a transistor structure, comprising the steps of:
- forming at least one recess in a semiconductor substrate;
- forming a first dielectric layer in the recess;
- forming a conductive block in a bottom portion of the recess;
- forming a liner mask covering an upper portion of the first dielectric layer in the recess;
- removing a portion of the first dielectric layer and the semiconductor substrate not covered by the liner mask to form a bulge-shaped depression in the semiconductor substrate;
- and
- forming a bulge-shaped dielectric structure filling the depression.
4 more elements
Dependencies are inferred from the claim text.