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US 2012/0235215 A1Published application
Performance enhancement in transistors by reducing the recessing of active regions and removing spacers
AssigneeGlobalfoundries Inc.
InventorsStefan Flachowsky, Jan Hoentschel
Life of this patent
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Abstract
Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.
Claims20
A method of forming a semiconductor device, the method comprising:
- forming a protective liner above an active region and a gate electrode structure formed on said active region, said gate electrode comprising a dielectric cap layer;
- forming drain and source extension regions in said active region in the presence of said protective liner;
- forming a spacer structure on said protective liner;
- removing an exposed portion of said protective liner by using said spacer structure as an etch mask;
- and
- forming drain and source regions by forming deep drain and source areas in said active region in the presence of said spacer structure.
3 more elements
A method, comprising:
- forming a protective liner above an active region of a transistor, said protective liner covering a gate electrode structure formed on said active region;
- forming drain and source extension regions by incorporating a drain and source dopant species in said active region through said protective liner;
- forming a spacer element on sidewalls of said gate electrode structure;
- forming drain and source regions in said active region by using said spacer element as an implantation mask;
- and
- removing said spacer element and a dielectric cap layer of said gate electrode structure after forming said drain and source regions.
3 more elements
A semiconductor device, comprising:
- an active region formed above a substrate;
- a gate electrode structure formed on said active region, said gate electrode structure comprising an electrode material and a gate dielectric layer including a high-k dielectric material;
- a protective liner having a first portion formed on sidewalls of said electrode material and said gate dielectric layer, said protective liner having a second portion formed on said active region;
- drain and source regions formed in said active region;
- and
- a strain-inducing dielectric material formed adjacent to and in contact with said protective liner.
3 more elements
Dependencies are inferred from the claim text.