Semiconductor structure with a stressed layer in the channel and method for forming the same

Abstract

The present invention provides a semiconductor structure with a stressed layer in the channel and method for forming the same. The semiconductor structure comprises a substrate; a gate stack, including a gate dielectric layer formed over the substrate, gate layer formed over the gate dielectric layer, a source region and a drain region formed in the substrate by both sides of the gate stack; one or more spacers formed on both sides of the gate stack; and an embedded stressed layer formed under the gate stack in the substrate. In the embodiments of the present invention, the carrier mobility can be effectively increased by the embedded stressed layer added in the channel under the gate stack, so that the driving current of transistors is improved. Moreover, the technological process for forming this embedded stressed layer in the present invention has a lower thermal budget, which therefore assists in maintaining a higher stress level in the channel region. Besides, apart from the advantage in the aspect of stress, the embedded stressed layer in the channel can further decrease the diffusion/invasion of B (boron) from the heavily doped source and drain regions.

Dependencies are inferred from the claim text.