Mask level reduction for mofet

A method of fabricating a thin film transistor and in-plane-switch LCD electrodes with six patterning/masking operations, the method comprising the steps of:

• providing a substrate with a surface;
• a first patterning/masking operation including patterning gate metal on the surface of the substrate to define a thin film transistor gate and contacts/leads for external electrical connections to the thin film transistor and in-plane-switch;
• forming a layer of gate dielectric over the gate and the contacts/leads and surrounding substrate surface;
• depositing a layer of semiconducting metal oxide on the layer of gate dielectric;
• a second patterning/masking operation including patterning a channel protection layer on the semiconducting metal oxide overlying the gate, the channel protection layer being patterned to define a channel area in the semiconducting metal oxide above the gate and to expose the remaining semiconducting metal oxide;
• depositing at least a source/drain metal layer on the channel protection layer and a portion of the exposed semiconducting metal oxide defining an in-plane-switch area;
• a third patterning/masking operation including etching through the source/drain metal layer to the channel protection layer above the gate to separate the source/drain metal layer into thin film transistor source and drain terminals, and etching through the semiconducting metal oxide layer over the contacts/leads;
• a fourth patterning/masking operation including patterning an organic dielectric material on the thin film transistor source and drain terminals and at an opposed side of the first electrode for the in-plane-switch;
• using the patterned organic dielectric material, etching through the source/drain metal layer in the in-plane-switch area to expose the semiconducting metal oxide and define a first electrode for an in-plane-switch;
• depositing a passivation layer on the patterned organic dielectric material and the first electrode for the in-plane-switch;
• a fifth patterning/masking operation including etching vias through the passivation layer and the layer of gate dielectric into communication with the contacts/leads;
• and
• a sixth patterning/masking operation including patterning a layer of transparent electrically conductive material on the passivation layer defining a second electrode for the in-plane-switch overlying the first electrode and through the vias into contact with the contacts/leads.

A thin film transistor and in-plane-switch LCD electrodes constructed for incorporation into an AMLCD comprising:

• a substrate with a surface;
• gate metal patterned on the surface of the substrate defining a thin film transistor gate;
• a layer of gate dielectric positioned over the gate and surrounding substrate surface;
• a layer of semiconducting metal oxide positioned on the layer of gate dielectric;
• a channel protection layer on the semiconducting metal oxide overlying the gate, the channel protection layer being patterned to define a channel area in the semiconducting metal oxide above the gate and to expose the remaining semiconducting metal oxide;
• at least a source/drain metal layer on the channel protection layer and a portion of the exposed semiconducting metal oxide defining an in-plane-switch area spaced laterally from the channel area and the source/drain metal layer;
• the source/drain metal layer being separated into thin film transistor source and drain terminals;
• an organic dielectric material positioned on the thin film transistor source and drain terminals and at an opposed side of the in-plane-switch area;
• the semiconducting metal oxide defining a first electrode for an in-plane-switch in the in-plane-switch area;
• a passivation layer positioned on the organic dielectric material and the first electrode for the in-plane-switch;
• and
• a layer of transparent electrically conductive material positioned on the passivation layer defining a second electrode for the in-plane-switch overlying the first electrode.