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AssigneesGlobal Unichip Corporation, National Taiwan University, Taiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Jen-Yang Wen, Chien-Mo Li
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In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.
A method for adjusting a test clock domain during a layout of an integrated circuit, wherein the integrated circuit comprises a plurality of scan cells, the plurality of scan cells comprise at least a plurality of first scan cells and a plurality of second scan cells, the plurality of first scan cells are arranged to be on a first scan chain and are tested by a first test clock, the plurality of second scan cells are arranged to be on a second scan chain and are tested by a second test clock different from the first test clock, and the layout of the integrated circuit comprises a plurality of regions, and the method comprises:
A method for creating a test clock domain during a layout of an integrated circuit, wherein the integrated circuit comprises a plurality of scan cells, the plurality of scan cells comprise at least a plurality of first scan cells and a plurality of second scan cells, the plurality of first scan cells are arranged to be on a first scan chain and are tested by a first test clock, the plurality of second scan cells are arranged to be on a second scan chain and are tested by a second test clock different from the first test clock, and the layout of the integrated circuit comprises a plurality of regions, and the method comprises:
A computer readable medium storing a test clock domain adjustment code, wherein the test clock domain adjustment code is utilized for adjusting test clock domains of a layout of an integrated circuit, the integrated circuit comprises a plurality of scan cells, the plurality of scan cells comprise at least a plurality of first scan cells and a plurality of second scan cells, the plurality of first scan cells are arranged to be on a first scan chain and are tested by a first test clock, the plurality of second scan cells are arranged to be on a second scan chain and are tested by a second test clock different from the first test clock, and the layout of the integrated circuit comprises a plurality of regions, and when the test clock domain adjustment code is executed by a processor, the test clock domain adjustment code executes the following steps:
Dependencies are inferred from the claim text.