Hierarchical error correction for large memories

A memory subsystem comprising:

• a data memory storing data in one or more memory regions, wherein each memory region comprises a plurality of unique memory segments;
• and
• an error control circuit, coupled to the data memory, and comprising
• a first level error detection and correction logic configured to
• determine a presence of data errors for each segment of a memory region, and
• for each memory segment, if the data error is a first type of error correct the data error in the memory segment, and if the data error is a second type of error set a flag associated with the memory segment, and
• a second level error detection and correction logic configured to
• determine if the data error is a third type of error if a flag is set for only one memory segment, and
• correct the data error for the memory region if the data error is not the third type of error.

A cache memory subsystem comprising:

• a data memory storing data in one or more cache lines, wherein
• each cache line comprises a plurality of unique double word segments;
• and
• an error control circuit, coupled to the data memory, and comprising
• a first level error detection and correction logic configured to
• determine a presence of data errors for each double word segment of a cache line when data from the cache line is accessed, and
• for each double word segment, if the data error is a single bit error then correct the single error in the double word segment, and if the data error is a double bit error then set a flag associated with the double word segment, and
• a second level error detection and correction logic configured to
• determine if the data error is a triple bit error in the cache line if a flag is set for only one double word segment, and
• correct the data error for the memory region if the data error is not a triple bit error.