Dynamic core selection for heterogeneous multi-core systems

A heterogeneous multi-core processing system comprising:

• an integrated circuit including
• a first processing core of a first type adapted to execute a program code;
• a second processing core of a second type adapted to execute the program code, the first type being different than the second type;
• and
• a code distribution module adapted to monitor performance and collect statistics of the first processing core executing the program code, predict the performance of executing the program code on the second processing core based at least in part on the monitored performance and collected statistics of the first processing core;
• and when the predicted performance of executing the program code on the second processing core is better than the performance of the first processing core executing the program code, switch execution of the program code from the first processing core to the second processing core.

A method of dynamically switching cores on a heterogeneous multi-core processing system comprising:

• executing program code on a first processing core of the heterogeneous multi-core processing system for a first number of cycles, the first processing core being of a first type;
• signaling power up of a second processing core of the heterogeneous multi-core processing system, the second processing core being of a second type, different than the first type;
• collecting a first performance metric of the first processing core executing the program code for a second number of cycles;
• when the first performance metric is better than a previously determined core performance metric, signaling power down of the second processing core and continuing execution of the program code on the first processing core;
• and
• when the first performance metric is not better than the previously determined core performance metric, switching execution of the program code from the first processing core to the second processing core and collecting a second performance metric of the second processing core executing the program code for the second number of cycles.

A heterogeneous multi-core processing system comprising:

• an integrated circuit including
• a first processing core of a first type adapted to execute a program code;
• a second processing core of a second type adapted to execute the program code, the first type being different than the second type;
• and
• a code distribution module adapted to cause execution of the program code on the first processing core for a first number of cycles, to signal power up of the second processing core, and to collect a first performance metric of the first processing core executing the program code for a second number of cycles;
• wherein when the first performance metric is better than a previously determined core performance metric, the code distribution module is adapted to signal power down of the second processing core and continue execution of the program code on the first processing core;
• and
• wherein when the first performance metric is not better than the previously determined core performance metric, the code distribution module is adapted to switch execution of the program code from the first processing core to the second processing core and collect a second performance metric of the second processing core executing the program code for the second number of cycles.