Shared-Variable-Based (SVB) Synchronization Approach for Multi-Core Simulation
AssigneeNational Tsing Hua University
InventorsCheng-Yang FU, Meng-Huan Wu, Ren-Song Tsay
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Abstract
The present invention discloses a shared-variable-based (SVB) approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach, synchronizing at either every cycle or memory access, gives accurate simulation results, it has poor performance due to huge simulation overloads. In the present invention, timing synchronization is only needed before shared variable accesses in order to maintain accuracy while improving the efficiency in the proposed shared-variable-based approach.
Claims20
A Shared-Variable-Based (SVB) synchronization approach for multi-core simulation comprising:
- a multi-core system containing an external memory and a plurality of cores, wherein each said core has a local cache;
- a parallel program containing a plurality of local variables and a plurality of shared variables, and running on said multi-core system;
- and
- only said shared variables residing on said local caches of said multi-core system require a timing synchronization and coherence action during simulation.
A Shared-Variable-Based (SVB) synchronization approach for multi-core simulation comprising:
- a multi-core system containing an external memory and a plurality of cores, wherein each said core has a local cache;
- a parallel program containing a plurality of local variables and a plurality of shared variables, and running on said multi-core system;
- a scheduler queuing and re-scheduling a plurality of timing synchronization and coherence actions during simulation;
- and
- only said shared variables residing on said local caches of said multi-core system require said timing synchronization and coherence action during simulation.
Dependencies are inferred from the claim text.