System and method of bypassing unrounded results in a multiply-add pipeline unit

A system comprising:

• a memory;
• and
• a processor coupled to the memory, wherein the processor comprises:
• a plurality of encoders coupled to receive input corresponding to a source operand, wherein one or more of the plurality of encoders do not receive a source operand input for a given operation, wherein a first encoder of the one or more encoders is configured to receive a rounding correction signal as an input;
• a multiplexer configured to:
• receive a select signal conveyed from the first encoder;
• and
• receive one or more rounding correction values as data inputs;
• wherein in response to detecting the rounding correction signal indicates the source operand represents an unrounded result of the prior operation which requires rounding, the first encoder is configured to select for conveyance from the first multiplexer a rounding correction value.

A method for implementing a multiply operation, the method comprising:

• coupling a source operand as input to a plurality of encoders, wherein one or more of the plurality of encoders do not receive a source operand input for a given operation;
• receiving at a first encoder of the one or more encoders a rounding correction signal as an input;
• receiving at a multiplexer a select signal conveyed from the first encoder, and one or more rounding correction values as data inputs;
• the first encoder selecting for conveyance from the first multiplexer a rounding correction value, in response to detecting the rounding correction signal indicates the source operand represents an unrounded result of the prior operation which requires rounding.