Method of forming multilayer capacitors in a printed circuit substrate

A method of forming a multilayer capacitor within a laminated circuit packaging structure, the steps comprising:

• a) providing a copper-clad dielectric substrate;
• b) etching a pattern of electrically conductive traces in a copper surface of said copper-clad dielectric substrate;
• c) laminating a photoimageable dielectric sheet over said electrically conductive traces;
• d) exposing and developing said photoimageable dielectric sheet to expose at least a portion of said electrically conductive traces;
• e) plating additional copper onto said electrically conductive traces;
• and
• f) dispensing a capacitor-forming material into an exposed space in aid electrically conductive trace, substantially filling said exposed space.

A method of forming a multilayer capacitor within a laminated circuit packaging structure, the steps comprising:

• a) providing a dielectric substrate having a predetermined thickness;
• b) forming a trench having a predetermined depth in a first major surface of said dielectric substrate;
• c) depositing a pattern of electrically conductive traces on a lower surface of said trench, said pattern of electrically conductive traces having a thickness substantially equal to said predetermined trench depth;
• and
• d) dispensing a capacitor-forming material into an exposed space in said pattern of electrically conductive material, substantially filling said exposed space.

A method of forming a multilayer capacitor within a laminated circuit packaging structure, the steps comprising:

• a) providing a dielectric substrate having a predetermined thickness;
• b) forming a trench having a predetermined depth in a first major surface of said dielectric substrate;
• c) depositing a pattern of electrically conductive traces on a lower surface of said trench, said pattern of electrically conductive traces having a thickness less than said predetermined trench depth;
• d) plating additional copper onto said electrically conductive traces;
• and
• e) dispensing a capacitor-forming material into an exposed space in said pattern of electrically conductive material, substantially filling said exposed space.

A method of forming a multilayer capacitor within a laminated circuit packaging structure, the steps comprising:

• a) providing a dielectric substrate having a pattern of electrical conductors on a major surface thereof and a photoimageable dielectric laminated to said major surface;
• b) developing said photoimageable dielectric to expose at least a portion of said pattern of electrical conductors;
• c) plating copper onto said exposed portion of said pattern of electrical conductors to a thickness such that the upper surface of said plated copper is substantially coplanar with a top surface of a remaining portion of said photoimageable dielectric;
• and
• d) dispensing a capacitor-forming material into an exposed space in said pattern of electrical conductors, substantially filling said exposed space.