Method and apparatus for using entropy in ant colony optimization circuit design from high level synthesis

A non-transitory computer-readable medium storing instructions thereon, the instructions when executed by a processor causing the processor to:

• select an operation to be performed by a circuit;
• represent, through a data flow graph having edges and nodes, a plurality of hardware components for performing the operation;
• simulate a plurality of solutions for performing the operation, each solution corresponding to a hardware component combination represented as a path on the data flow graph;
• determine a cost for each solution of the plurality of solutions, the cost including a number of edges and nodes traversed on the data flow graph and a supplemental sub-integer cost;
• and
• select a solution from among the plurality of solutions, the selected solution having a lowest determined cost.

A digital processing system comprising:

• means for selecting an operation to be performed by a circuit;
• means for representing, through a data flow graph having edges and nodes, a plurality of hardware components for performing the operation;
• means for simulating a plurality of solutions for performing the operation, each solution corresponding to a hardware component combination represented as a path on the data flow graph;
• means for determining a cost for each solution of the plurality of solutions, the cost including a number of edges and nodes traversed on the data flow graph and a supplemental sub-integer cost;
• and
• means for selecting a solution from among the plurality of solutions, the selected solution having a lowest cost.

An apparatus comprising:

• a memory to store a data flow graph representing a plurality of hardware components for performing at least one operation, the data flow graph having edges and nodes;
• a solution simulator coupled to the memory to receive the data flow graph and to simulate a plurality of solutions for performing the operation as hardware component combinations represented as paths on the data flow graph;
• a cost estimator coupled to the solution simulator to receive the solutions and to determine a cost for each solution, the cost including a number of edges and nodes traversed on the data flow graph and a supplemental sub-integer cost;
• and
• a solution selector coupled to the cost estimator to receive the estimated costs and to select a solution with the lowest cost as a hardware component combination for a circuit.