Ram single event upset (seu) method to correct errors

A method of reducing single event upset (SEU) errors in memory systems with an error detection and correction (EDAC) circuit, the method comprising:

• retrieving first data and parity information from a first memory device;
• retrieving second data and parity information from a second memory device, wherein the second data is redundant to the first data retrieved from the first memory device;
• calculating whether the parity of the first data is ‘good’ or ‘bad’ based on the retrieved first data and parity information;
• calculating whether the parity of the second data is ‘good’ or ‘bad’ based on the retrieved second data and parity information;
• detecting differences between the first data the second data, and between the first parity information and the second parity information;
• and
• selecting either the first data or the second data for provision to a data bus based on the calculated parity of the first data and the second data and the differences between the first data and the second data, and between the first parity information and the second parity information.

A redundant memory system comprising:

• a first memory device for storing first data and parity information;
• a second memory device for storing second data and parity information redundant to the first data and parity information;
• and
• an error detection and correction (EDAC) circuit that during write operations encodes parity information in data being written to the first memory device and the second memory device and during read operations determines whether to select data from the first memory device or the second memory device to provide onto a data bus, the EDAC circuit comprising:
• first parity check logic that calculates whether parity is ‘good’ or ‘bad’ in the received first data and parity information;
• second parity check logic that calculates whether parity is ‘good’ or ‘bad’ in the received second data and parity information;
• bit comparison logic that detects differences between the first data and parity information and the second data and parity information;
• and
• data select logic that selects either the first data or the second data for provision to the data bus based on the calculated parity of the first data and the second data and the differences between the first data and the second data, and between the first parity information and the second parity information.