Hardware Dynamic Cache Power Management

A system comprising:

• one or more processors;
• a cache coupled to the one or more processors;
• and
• a bridge coupled to the cache and configured to couple to one or more peripherals, wherein the bridge comprises a plurality of registers that are programmable with data representing a first plurality of operations to be performed prior to powering down the cache and a second plurality of operations to be performed during a power up of the cache, and wherein the bridge is configured to perform the first plurality of operations in response to a power down event for the cache and to perform the second plurality of operations in response to a power up event for the cache.

A method comprising:

• detecting that a cache is to be powered up in a system including one or more processors coupled to the cache, wherein the one or more processors are powered down at a time of the detecting;
• issuing a request to a bridge that is coupled to the cache and one or more peripherals;
• and
• the bridge responding to the request by performing a plurality of operations stored in the bridge to initialize one or more configuration registers in the cache.

A system comprising:

• one or more processors;
• a cache coupled to the one or more processors, the cache comprising a plurality of configuration registers that are programmable to control operation of the cache;
• a power manager coupled to the processors and the cache, wherein the power manager is configured to control power up and power down of the processors and the cache;
• and
• a bridge coupled to the cache and the power manager, wherein the bridge is configured to couple to one or more peripherals, and wherein the bridge comprises a plurality of registers programmable with address and data pairs representing register writes to the plurality of configuration registers, and wherein the bridge is configured to perform at least a first register write to a first configuration register of the plurality of configuration registers in response to a power down event for the cache signalled by the power manager, and wherein the bridge is configured to perform at least a second register write to a second configuration register of the plurality of configuration register in response to a power up event for the cache.