Cache memory controller and method for replacing a cache block
AssigneeSejong University Industry Academy Cooperation Foundation
InventorGi Ho Park
Life of this patent
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Abstract
The present disclosure relates to a cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller including a content modification status monitoring unit for monitoring whether some of the blocks arranged in the same set of the cache memory have been modified in contents, and a cache block replacing unit for replacing a block, which has not been modified in contents, if some of the blocks arranged in the same set have been modified in contents.
Claims11
A cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller comprising:
- a write buffer monitoring unit configured to monitor whether a number of cache blocks stored in the write buffer is at least a predetermined threshold;
- a content modification status monitoring unit configured to monitor whether some of the blocks arranged in the same set of the cache memory have been modified in contents;
- and
- a cache block replacing unit configured to replace a lower memory block fetched as a result of cache miss, when the number of the cache blocks stored in the write buffer is at least the threshold, and some of the blocks arranged in the same set have not been modified in contents, with the blocks that have not been modified in contents.
A method for replacing a cache block of a set-associative cache memory, in which two or more blocks are arranged in the same set, the method comprising:
- monitoring cache blocks stored in the write buffer upon cache miss;
- determining whether a number of the stored cache blocks is at least a threshold;
- determining whether a data array includes a dirty block, based on a dirty bit of a tag array;
- and
- replacing a lower memory block fetched as a result of the cache miss with a clean block, if the number of the cache blocks stored in the write buffer is at least a threshold, and some of the two or more blocks arranged in the same set include a dirty block.
(canceled)
Dependencies are inferred from the claim text.