Circuit and method for determining memory access, cache controller, and electronic device
AssigneeFujitsu Semiconductor Limited
InventorKazuhiko OKADA
Life of this patent
Estimating the term…
Abstract
A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination.
Claims12
A memory access determination circuit comprising:
- a counter that switches between a first reference value and a second reference value in accordance with a control signal and generates a count value based on the first reference value or the second reference value;
- a controller that performs a cache determination based on an address corresponding to the count value and generates the control signal in accordance with the cache determination;
- and
- a changing unit that changes the second reference value in accordance with the cache determination.
A cache controller comprising:
- a cache determination unit that performs a cache determination, based on an address corresponding to a count value output from a counter in accordance with a reference value, and outputs a control signal;
- and
- a changing unit that changes the reference value with the control signal so that a cache hit rate increases when the cache determination indicates a cache miss.
A method for determining memory access, the method comprising:
- switching between a first reference value and a second reference value in accordance with a control signal;
- generating a count value based on the first reference value or the second reference value;
- performing a cache determination based on an address corresponding to the count value;
- generating the control signal in accordance with the cache determination;
- and
- changing the second reference value in accordance with the cache determination.
An electronic device comprising:
- a main memory;
- a cache memory that operates at a higher speed than the main memory;
- a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value;
- a controller that performs a cache determination based on an address corresponding to the count value and generates the control signal in accordance with the cache determination;
- and
- a changing unit that changes the second reference value in accordance with the cache determination.
Dependencies are inferred from the claim text.