US 2012/0084473 A1 · METHOD AND BUS SYSTEM FOR EQUALIZING DATA INFORMATION TRAFFIC AND DECODER

Abstract

In the field of integrated circuit (IC) design, a method and a bus system for equalizing data information traffic and a decoder are provided. The method includes: receiving data information sent by a device, and allocating at least two transmission interfaces for the data information according to a decoding result of decoding a designated bit in the data information, where the data information carries a device ID, and the designated bit position occupied at least one bit in the device ID; judging whether the data information traffic of the at least two transmission interfaces is balanced; and when the data information traffic of the at least two transmission interfaces is not balanced, switching the designated bit position, and decoding the designated bit after switching, so as to balance the traffic of the at least two transmission interfaces. The bus system includes an interface allocation module, a traffic judging module and a bit position switching module. The decoder includes a decoding module and a designated bit position switching module.

Claims13

Dependent claims

A method for equalizing data information traffic, comprising:

receiving data information sent by a device, and allocating at least two transmission interfaces for the data information according to a decoding result of decoding a bit value on a designated bit position in the data information, wherein the data information carries a device ID, and the designated bit position occupies at least one bit in the device ID;
judging whether the data information traffic of the at least two transmission interfaces is balanced;
and
when the data information traffic of the at least two transmission interfaces is not balanced, switching the designated bit position, and decoding bit values on the designated bit position after switching, so as to balance the traffic of the at least two transmission interfaces.

1 more element

A bus system for equalizing data information traffic, comprising:

an interface allocation module, configured to allocate transmission interfaces for data information according to a decoding result of decoding a bit value on a designated bit position in the data information, wherein the data information carries a device ID, and the designated bit position occupies one bit position in the device ID;
a traffic judging module, configured to judge whether the data information traffic of the transmission interfaces is balanced;
and
a bit position switching module, configured to switch the designated bit position when the data information traffic of the transmission interfaces is not balanced, and decode a bit value on the designated bit position after switching, so as to balance the traffic of the transmission interfaces.

1 more element

Dependencies are inferred from the claim text.

Method and bus system for equalizing data information traffic and decoder

Life of this patent

Method and bus system for equalizing data information traffic and decoder

Life of this patent

Abstract

Claims13