Passgate for Dynamic Circuitry

A circuit for a memory array, the circuit comprising:

• a discharge circuit;
• a first bit line coupled to the discharge circuit, wherein the discharge circuit is configured to, during an evaluation phase, discharge the first bit line responsive to a first condition;
• a first passgate transistor having a first terminal coupled to the first bit line and a gate terminal coupled to a static voltage, wherein the first passgate transistor is configured to remain active during operation responsive to the static voltage;
• and
• a precharge circuit coupled to a second terminal of the first passgate transistor, wherein the precharge circuit is configured to, during a precharge phase, precharge the first bit line via the first passgate transistor.

A memory circuit comprising:

• a plurality of first bit lines;
• a plurality of precharge circuits, wherein each of the plurality of precharge circuits is coupled to a corresponding one of the plurality of first bit lines;
• a plurality of gate transistors, wherein each of the wherein each of the plurality of gate circuits is coupled to a corresponding one of the plurality of first bit lines, and wherein a gate terminal of each of the plurality of gate transistors is coupled to a first fixed voltage such that each of the plurality of gate transistors remain active during operation;
• and
• a plurality of second bit lines coupled to each of the plurality of gate transistors;
• wherein each of the plurality of precharge circuits is configured to precharge its corresponding first bit line to a supply voltage during a first portion of a clock phase and further configured to cause its corresponding second bit line to be precharged to a voltage that is less than the supply voltage by at least a threshold voltage of the corresponding gate transistor.