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US 2012/0075936 A1Published application
Bit line negative potential circuit and semiconductor storage device
AssigneeKabushiki Kaisha Toshiba
InventorYuki Fujimura
Life of this patent
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Abstract
According to one embodiment, a bit line negative potential circuit includes a bit line capacitance compensation capacitor which compensates the capacitance of a bit line and a peripheral capacitance compensation capacitor which compensates the peripheral capacitance of the bit line. After the bit line is switched to a low potential, the bit line is driven based on a charging voltage of the bit line capacitance compensation capacitor and the peripheral capacitance compensation capacitor.
Claims20
A bit line negative potential apparatus, comprising:
- a first capacitor;
- a second capacitor;
- a first charge circuit configured to charge the first capacitor with an electrical charge corresponding to a capacitance of a bit line;
- a second charge circuit configured to charge the second capacitor with an electrical charge corresponding to a first voltage;
- and
- a switching circuit configured to drive the bit line based on a charging voltage of the first and second capacitors after the bit line is switched to a low potential.
3 more elements
A semiconductor storage device, comprising:
- a memory cell array comprising memory cells arranged in a matrix in row and column directions;
- a word line configured to select a row of the memory cell array;
- a row decoder configured to select the word line based on a row address;
- a bit line configured to select a column of the memory cell array;
- a column selector configured to select the bit line;
- a sense amplifier configured to sense data stored in the memory cell, based on a signal read on the bit line from the memory cell;
- and
- a bit line negative potential apparatus configured to set a low potential of the bit line to a negative potential at the time of writing in the memory cell and to set the negative potential based on a capacitance of the bit line and a parasitic capacitance around the bit line.
5 more elements
Dependencies are inferred from the claim text.